SiLabs aims at 56Gbit/s comms with low-jitter clock chips
- Release on:2018-06-26
Si5391 is an ‘any-frequency’ clock generator with up to 12 outputs and sub-100fs RMS phase jitter.
A precision calibrated version (‘P-grade’) typically achieves 69fs RMS phase jitter and can create the primary frequencies needed in 56Gbit/s serdes designs. The firm describes it as a ‘true sub-100 fs clock-tree-on-a-chip’ meeting 56G PAM-4 reference clock jitter requirements with margin.
Si5395/4/2 are jitter attenuators for Internet infrastructure that can generate any combination of output frequencies from any input frequency while delivering 90fs RMS phase jitter. Once again, P-grade devices offer 69fs RMS typical phase jitter.
Si56x ‘Ultra Series’ VCXO and XO family is customisable to any frequency up to 3GHz, supporting twice the operating frequency range of previous Silicon Labs VCXO products with half the jitter, according to the firm.
They come in single, dual, quad, and I2C-programmable options in 5 x 7mm and 3.2 x 5mm versions. Using standard packaging means they will drop inot some sockets occupied by earlier XO, VCXOs and VCSOs. Typical phase jitter is as low as 90fs.
Si54x Ultra Series XO family is for applications requiring tighter stability and guaranteed long-term reliability, such as optical transport networking (OTN), broadband equipment, data centres and industrial systems.
They are purpose-built for 56Gbit/s PAM-4 (four-level pulse-amplitude modulation) to increase the bit rate per channel while keeping the bandwidth constant. Typical phase jitter is as low as 80 fs.